It is expected that nonvolatile, byte-addressable memory (NVM) will soon be commonplace. However, registers and caches are expected to remain transient. In the event of a power failure, NVM content will be preserved, but data stored in the cache and processor will be lost. Since main memory is customarily seen through the filter of current cache contents, data must be carefully managed in NVM to ensure consistency in the wake of a crash.

In this work, we introduce a new memory persistency model, explicit epoch persistency, that builds upon and generalizes prior work. Our model captures both hardware buffering and fully relaxed consistency, and subsumes both existing and proposed instruction set architectures. Using the persistency model, we present an automated transform to convert any linearizable, nonblocking concurrent object into one that is also correct for nonvolatile memory.

While this transform is correct, it is not necessarily performant. To reduce this overhead, we developed a new design paradigm that we call periodic persistence. In a periodically persistent data structure, updates are made “in place,” but can safely leak back to memory in any order, because only those updates that are known to be valid will be heeded during recovery. To guarantee forward progress, we periodically force a write-back of all dirty data in the cache, ensuring that all “sufficiently old” updates have indeed become persistent, at which point they become semantically visible to the recovery process. Experiments with a prototype implementation suggest that periodic persistence can offer substantially better performance than either file-based or incrementally persistent (per-access write-back) alternatives.